1. Field of the Invention
The present invention relates to a bus transfer apparatus provided at a communication node included in a computer network, and more particularly to a bus transfer apparatus for receiving and repeating a packet.
2. Description of the Related Art
Components included in computer systems are connected with each other via a bus such as a cable to transfer information between each component. This interconnection of the components of the computer systems leads to the formation of a network.
FIG. 9 is a diagram showing a structure of a component 60 included in a computer system. The component 60 is connected to other components via buses 66 and 67. The component 60 may be a disk drive, a keyboard, a printer, a computer itself, or the like. The buses 66 and 67 may be cables.
The component 60 includes a communication node 61 which performs data communication in accordance with a common communication protocol for a network; a device 62; and a device control apparatus 63 for controlling the device 62. When the component 60 is a disk drive, the device control apparatus 63 controls movement of a disk itself, or reading and writing of a disk.
The communication node 61 includes a protocol controller 64 and a bus transfer apparatus 65. The protocol controller 64 converts data (e.g., instructions) output from the device 62 to data having a format compliant with a communication protocol. The protocol controller 64 also converts transferred data having the format compliant with the communication protocol to data having a format which can be understood by the device 62. The bus transfer apparatus 65 controls data transfer on the buses 66 and 67 in accordance with the communication protocol.
In some networks, a port of a communication node is connected to a port of another communication node in a one-to-one correspondence. Tree-type networks and daisy-chain-type networks are known.
Such a connection structure of the communication nodes is defined by IEEE standard xe2x80x9c1394 Standard for a High Performance Serial Busxe2x80x9d. In this standard, a communication node receives a packet through a port and outputs the same packet as the received packet through another port. This operation is called a xe2x80x9crepeat operationxe2x80x9d. The repeat operation allows a packet to be transferred to all communication nodes existing on a network.
Hereinafter, the repeat operation will be described with reference to FIGS. 10A through 10C.
FIG. 10A is a diagram showing a plurality of communication nodes connected to each other via cables. In FIG. 10A, reference numerals 40, 41, 42, 43, and 44 indicate communication nodes. Reference numerals 401, 402, 403, 404, 405, 406, 407, 408, and 409 indicate ports of the communication nodes. Reference numerals 410, 411, 412, and 413 indicate cables.
FIG. 10B shows the repeat operation of the communication node 41. The communication node 40 transmits a packet from the port 401. The packet is received through the port 402 by the communication node 41. To transfer the packet received through the port 402 to the entire network, the communication node 41 outputs the same packet as the received packet from the port 404. The packet received through the port 402 is repeated to the port 404 by the repeat operation of the communication node 41. In FIG. 10B, arrows 420 and 421 indicate directions in which the packet is transferred. The port 403 of the communication node 41 is not connected to a cable. The received packet is not repeated to the port 403.
FIG. 10C shows the repeat operation of the communication node 42. A packet is received through the port 405. The packet is then repeated to the ports 406 and 407. This repeat operation allows the packet to be transferred to the communication nodes 43 and 44. In FIG. 10C, arrows 421, 422, and 423 indicate directions in which the packet is transferred.
As described above, each communication node performs the repeat operation. This allows a packet transmitted by a given communication node to be transferred to the entire network. A received packet is latched within a communication node and it is then output in synchronization with an internal clock signal. This leads to minimization of attenuation of a signal due to transmission.
FIG. 11 shows an example of a configuration of a conventional bus transfer apparatus. The conventional bus transfer apparatus shown in FIG. 11 includes a control circuit 30, a decoder 31, a synchronization circuit 32, an encoder 33, and a selector 34.
FIG. 12A shows a typical structure of a packet which. is input to the conventional bus transfer apparatus as an input signal. This packet is transferred between each communication node.
As shown in FIG. 12A, a packet includes a PREFIX portion 50 indicating the head of the packet, a DATA portion 51 storing data, and an END portion 52 indicating the end of the packet. The PREFIX portion 50, DATA portion 51, and END portion 52 of the packet are arranged in this order from the head of the packet.
Next, the operation of the conventional bus transfer apparatus when receiving a packet will be described with reference to FIG. 11.
An input signal is input to the control circuit 30 and the decoder 31.
The control circuit 30 constantly receives input signals on a cable and monitors the received signals. When the control circuit 30 receives the PREFIX portion 50 of a packet included in the input signal, the control circuit 30 outputs the PREFIX portion 50 to the selector 34 as a control signal. This triggers a repeat operation in which the packet is repeated to a port other than the receiving port.
The decoder 31 receives the PREFIX portion 50 of a packet included in the input signal. Then, the decoder 31 generates a clock signal which is to be used for receiving the DATA portion 51 of a packet (hereinafter referred to as a receiving clock signal). The decoder 31 latches data bits of the DATA portion 51 in synchronization with the receiving clock signal. The receiving clock signal may be generated by any method. In the IEEE 1394 standard, for example, the DATA portion 51 includes data and strobes supplementing the data. In this case, the receiving clock signal is generated by an exclusive OR of the data and strobe of the DATA portion 51.
The data bits latched in the decoder 31 are synchronized with a system clock signal used in a communication node by the synchronization circuit 32. Then, the data bits are output to the encoder 33.
The encoder 33 converts the DATA portion 51 to a predetermined format. The converted DATA portion 51 is output to the selector 34. The encoder 33 asserts a select signal to the selector 34 while the converted DATA portion 51 is being output to the selector 34. The asserted select signal indicates that the converted DATA portion 51 is being output to the selector 34.
The selector 34 normally selects a control signal output from the control circuit 30 and outputs the selected control signal as an output signal. When the select signal is asserted, the selector 34 selects the data bits output from the encoder 33 and outputs the selected data bits as an output signal.
In response to the select signal, the output signal of the selector 34 is switched from the PREFIX portion 50 to the DATA portion 51. Then, the control signal output from the control circuit 30 is switched from the PREFIX portion 50 indicating the head of a packet to the END portion 52 indicating the end of the packet. The switching of the control signal may be performed at any time during a time period when the encoder 33 is outputting the DATA portion 51. In the case of a concatenated packet in the IEEE 1394 protocol, for example, the last one bit of the DATA portion 51 decides which follows immediately after the DATA portion 51, the PREFIX portion 51 or the END portion 52. In such a case, the control circuit 30 monitors a signal indicating the end of data (hereinafter referred to as an end-of-data signal) which is output from the encoder 33 to determine whether to switch the control signal.
FIG. 12B shows a structure of a concatenated packet. As shown in FIG. 12B, a concatenated packet includes a concatenation of a plurality of DATA portions. One DATA portion is concatenated via a PREFIX portion with another DATA portion. The concatenated packet includes only one END portion which exists immediately after the last DATA portions.
The communication nodes belong to the respective domains which each have an independent clock signal. The period or phase of a clock signal varies among the communication nodes. When a communication node at the receiver has a clock signal different from that of a communication node at the transmitter, the communication node at the receiver recognizes the same packet as having a different length.
This point will be described with reference to FIGS. 13A and 13B.
FIG. 13A shows a configuration of a network for explanation. In FIG. 13A, reference numerals 70, 71, and 72 indicate communication nodes. Reference numerals 73 and 74 indicate cables.
FIG. 13B is a timing chart where the communication node 70 transmits a packet. In FIG. 13B, reference numeral 75 indicates a system clock signal used in the communication node 70; reference numeral 76 a signal on the cable 73 output from the communication node 70; reference numeral 77 a system clock signal used in the communication node 71; reference numeral 78 a signal output as a result from the latching and repeating of the signal on the cable 73 by the communication node 71; reference numeral 7a a PREFIX portion output from the communication node 70; reference numeral 7b a DATA portion output from the communication node 70; reference numeral 7c a PREFIX portion output as a result from the latching and repeating by the communication node 71; and reference numeral 7d a DATA portion output as a result from the latching and repeating by the communication node 71.
In the network shown in FIG. 13A, the communication node 70 transmits a packet. The communication node 71 then receives the packet and repeats the packet to the communication node 72.
It is now assumed that the communication node 70 begins to output a PREFIX portion at time t1 and then begins to output a DATA portion at time t2. When a system clock signal used in the communication node 71 has a longer period than the period of a system clock signal used in the communication node 70, the communication node 71 latches and repeats the PREFIX portion at a clock edge at time t3. The communication node 71 latches and repeats the DATA portion at a clock edge at time t4. When the system clock signal used in the communication node 70 has the same period as the period of the system clock signal used in the communication node 71, the PREFIX portion is repeated up to time t5. Due to the difference in a period, the time period len2 (3 clock cycles) during which the communication node 71 repeats the PREFIX portion becomes shorter than the time period len1 (4 clock cycles) during which the communication node 70 outputs the PREFIX portion.
As described above, as to the conventional bus transfer apparatus, there is a problem in that the repeat operation may cause the time period of the PREFIX portion of a packet to be shortened. In the daisy-chain type network, the repeat operation is repeated in a plurality of communication nodes, aggravating the above-described problem.
The bus transfer apparatus of this invention for receiving a packet and repeating the received packet, in which the packet includes a PREFIX portion indicating the head of the packet, a DATA portion storing data, and an END portion indicating the end of the packet, includes a control circuit for receiving the packet and outputting the PREFIX portion of the packet as a control signal; a counter for counting a time period during which the control circuit outputs the PREFIX portion, and outputting a counter full signal when the time period reaches a predetermined lower limit; an address pointer for determining a read address in response to the counter full signal; a data buffer for holding the DATA portion of the packet and outputting the DATA portion in accordance with the read address; an encoder for converting the DATA portion output from the data buffer to a predetermined format; and a first selector for selecting either, the PREFIX portion output from the control circuit or the DATA portion output from the encoder. The output signal from the first selector is switched from the PREFIX portion of the packet to the DATA portion of the packet after the counter full signal is output from the counter.
In one embodiment of this invention, the bus transfer apparatus further includes a receiving counter for storing the number of received packets; and a repeat counter for storing the number of repeated packets. The address pointer includes a plurality of address counters being selectively transitioned into an operating state in accordance with an output from the receiving counter; a second selector for selecting one of the plurality of address counters in accordance with an output from the repeat counter; an address holding circuit for holding an output from the second selector and outputting the output from the second selector as a read address in response to the counter full signal.
In one embodiment of this invention, the control circuit includes a first delay section for delaying the control signal; and a second delay section for delaying a trigger signal instructing initiation of counting.
In one embodiment of this invention, the control circuit further includes a comparison section for comparing an output from the receiving counter with an output from the repeat counter to determine whether repeat operation of the received packet is completed.
In one embodiment of this invention, the encoder outputs an end-of-data signal to the control circuit after converting the DATA portion to the predetermined format.
In one embodiment of this invention, the data buffer outputs a buffer empty signal to the address pointer after outputting all the DATA portion held in the data buffer.
In one embodiment of this invention, the address pointer renders the read address ineffective in response to the buffer empty signal.
Hereinafter, functions of the bus transfer apparatus will be described.
According to an aspect of this invention, the output signal from the selector of the bus transfer apparatus is switched from the PREFIX portion of a packet to the DATA portion of the packet after the counter outputs the counter full signal. The counter full signal is output when the time period during which the control circuit is outputting the PREFIX portion of the packet reaches the predetermined lower limit. This prevents the time period during which the control circuit is outputting the PREFIX portion of the repeated packet from becoming shorter than the lower limit. As a result, the lower limit of the time period during which the control circuit is outputting the PREFIX portion of the repeated packet is guaranteed.
According to another aspect of this invention, the address pointer includes a plurality of address counters. One of the plurality of address counters is selectively transitioned into an operating state. For this reason, even when a new packet is received before completion of the repeat operation, the lower limit of the time period during which the control circuit is outputting the PREFIX portion of the repeated packet is guaranteed.
According to still another aspect of this invention, the first delaying section for delaying output of the control signal and the second delaying section for delaying output of the trigger signal instructing the initiation of the counting are provided in the bus transfer apparatus. This prevents the time period during which the control circuit is outputting the PREFIX portion of the repeated packet from becoming longer than the upper limit. As a result, the upper limit of the time period during which the control circuit is outputting the PREFIX portion of the repeated packet is guaranteed.
Thus, the invention described herein makes possible the advantages of providing a bus transfer apparatus in which a lower limit of the time period of the PREFIX portion of a packet output by the repeat operation is guaranteed.